Publications
SECOND YEAR ACTIVITY
Publications
Paolo Magnone, Claudio Fiegna, Giuseppe Greco, Gaetano Bazzano, Enrico Sangiorgi, Salvatore
Rinaudo, “Modeling of Thermal Network in Silicon Power MOSFETs”,Proceedings of the IEEE 12th ULIS 2011, 14-16 March 2011, Cork, Ireland
G.Bazzano, D. G. Cavallaro, G. Greco, A. Grimaldi, S. Rinaudo, “Stress and Reliability of Power Devices: an Innovative Thermal Analysis Approach to Predict a Device’s Lifetime”, PCIM Europe 2011, Nuremberg, 17-19 may 2011.
G.Bazzano, D. G. Cavallaro, G. Greco, “An Analog Behavioral Thermal Macro-model Aimed at
Representing an Elementary Portion of a Discrete IGBT Power Device”, Proceedings of the IEEE 17th THERMINIC 2011, Paris (France), Sep 27-29, 2011.
F. Moschella, G. Gangemi , E.Macii, M. Rencz, S.Rinaudo, “The THERMINATOR Project: Midway
Achievements and Perspectives”, Proceedings of the IEEE 17th THERMINIC 2011, Paris (France), Sep 27-29, 2011.
Melikyan V., Durgaryan A., Petrosyan H. , Stepanyan A., “Power Efficient, Low Noise 2-5GHz Phase Locked Loop,” Proceedings of the 31st international scientific-technical conference “Electronics and nanotechnology”, Kiev, Ukraine, April 12-14, 2011.-pp. 66-71
Melikyan V., Poghosyan A., Durgaryan A., Petrosyan H., Simonyan M., “Method of Parametrical Optimization of Multi-Core Processors,” Proceedings of the 31st international scientific-technical conference “Electronics and nanotechnology”, Kiev, Ukraine, April 12-14, 2011.-pp. 126-130
Melikyan V., Petrosyan H., Durgaryan A., Topisirović D., “New Retention Flop Architecture with Phase Frequency Detection (PFD) Capabilities,” Proceedings of the 55th Electronics, Telecommunications, Computers, Automatic Control and Nuclear Engineering (ETRAN) Conference, Banja Vrućica, Serbia, 2011.-P.EL4.2-1-4
Melikyan V., Durgaryan A., Petrosyan H., Topisirović D., “A Fully Differential Phase-Frequency Detector Design for Low Noise Phase Locked Loop Applications,” Proceedings of the 55th Electronics, Telecommunications, Computers, Automatic Control and Nuclear Engineering (ETRAN) Conference, Banja Vrućica, Serbia, 2011.-P.EL4.3-1-4
Roldman R., Melikyan V., Babayan E., “Method of Electro-Thermal Co-Simulation of Integrated Circuits,” Proceedings of the 8th International Conference of “Semiconductor Micro- and Nanoelectronics”, Yerevan, Armenia, 2011.-P.207-213
Melikyan V., Durgaryan A., Petrosyan H., Melikyan N., ”Automatic PLL Activation Mechanism
from Power Gated State,” Proceedings of the 8th International Conference of “Semiconductor Micro- and Nanoelectronics”, Yerevan, Armenia, 2011.-P.214-217
Melikyan V., Eminyan N.S., Chobanyan S.G., Beglaryan N.H., “Design Method of Low-Leakage Hybrid 9T-SRAM,” Scientific journal of National Academy of Science and State Engineering University of Armenia. Vol. 64, N 3, Yerevan, Armenia, 2011.- pp. 265-274
Melikyan V., Durgaryan A., “Programmable Current Biasing for Low Noise Voltage Controlled Oscillators,” Proceedings of IEEE East-West Design & Test Symposium (EWDTS’11), Sevastopol, Ukraine, 2011.-P.47-50
Melikyan V., Roldman R., Babayan E., “Digital Circuits Verification with Consideration of Destabilizing Factors,” Proceedings of the 6th IEEE International Design and Test Workshop (IDT) in Conjunction with IEEE International Conference on Electronics, Circuits and Systems (ICECS), Beirut, Lebanon, 2011.-P.93-98
Sassone, A.; Wei Liu; Calimera, A.; Macii, A.; Macii, E.; Poncino, M.; "Modeling of thermally induced skew variations in clock distribution network", THERMINIC'11: IEEE Workshop on Thermal Investigations of ICs and Systems, pp.1-6, 27-29 Sept. 2011
Lingasubramanian, K.; Calimera, A.; Macii, A; Macii E.; Poncino, M.; "Sub-row sleep transistor insertion for concurrent clock-gating and power-gating," Lecture Notes in Computer Science, Springer, Vol. 5951, pp. 214-225, 2011, doi: 10.1007/978-3-642-24154-3_22
de Lima Silva, L. M.; Calimera, A.; Macii, A.; Macii, E.; Poncino, M.; "Power Efficient Variability Compensation Through Clustered Tunable Power-Gating," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.1, no.3, pp.242-253, Sept. 2011, doi: 10.1109/JETCAS.2011.2163689
Calimera, A.; Loghi, M.; Macii, E.; Poncino, M.; "Buffering of frequent accesses for reduced cache aging," GLSVLSI’11: ACM Great Lakes symposium on VLSI, pp. 295-300, May 2011
Rinaudo, S.; Gangemi, G.; Calimera, A.; Macii, A.; Poncino, M.; , "Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems," DATE’11: Design, Automation & Test in Europe Conference & Exhibition, pp.1-2, 14-18 March 2011
Calimera, A.; Loghi, M.; Macii, E.; Poncino, M.; , "Partitioned cache architectures for reduced NBTI-induced aging," DATE’11: Design, Automation & Test in Europe Conference & Exhibition, pp.1-6, 14-18 March 2011
Steve Stoffels, Denis Marcon, Karen Geens, Xuanwu Kang, Geert Van Der Plas, Marleen Van Hove and Stefaan Decoutere, “High Temperature Calibration of a Compact Model for GaN-on-Si Power Switches”, Therminic 2011, Paris, 27-29 September 2011, pp. 159-163
Oprins, H.; Cherman, V.; Vandevelde, B.; Stucchi, M.; Van der Plas, G.; Marchal, P. and Beyne, E., “Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips,” 27th Annual IEEE Thermal Measurement, Modeling and Management Symposium (SEMI-Therm), March 20-24, 2011, 131-137.
Oprins, H.; Srinivasan, A.; Cupak, M.; Cherman, V.; Torregiani, C.; Stucchi, M.; Vandevelde, B.; Van der Plas, G.; Marchal, P. and Cheng, E., “Fine grain thermal modelling and experimental validation of 3D-ICs,” Microelectronics Journal, Vol. 42 (4), April 2011, pp. 572-578.
A. Burenkov, J. Lorenz, “Self-heating effects in nano-scaled MOSFETs and thermal aware compact models,” THERMINIC, 17th International Workshop on Thermal investigations of ICs and Systems, Paris, France, 27-29 Sept. 2011, EDA Publishing, Collection of papers, pp. 17-18.
R. Jancke, S. Reitz, A. Heinig, R. Martin, J. Stole, A. Wilde, “Thermal modeling of 3D stacks for floorplanning,” THERMINIC, 17th International Workshop on Thermal investigations of ICs and Systems, Paris, France, 27-29 Sept. 2011, EDA Publishing, Collection of papers, pp. 153-158.
A. Timár, M. Rencz "Studying the influence of chip temperatures on timing integrity." In: 12th IEEE Latin-American Test Workshop. Brazil, 27-30. 03. 2011.
A Timár, M. Rencz "Studying the Influence of Chip Temperatures on Timing Integrity Using Improved Power Modeling." JOURNAL OF LOW POWER ELECTRONICS 7: pp. 1-10. (2011)
A Timár, Gy. Bognár, M. Rencz "Improved power modeling in logi-thermal simulation." In: 17th International Workshop on Thermal investigations of ICs and Systems. Paris, Paris, France, 27-29. 09. 2011.
Gergely Nagy, András Poppe "A Novel Simulation Environment Enabling Multilevel Power Estimation of Digital Systems." In: Proceedings of the 17th International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC'11). Paris, France, 27-29. 09. 2011, pp. 149-152. (ISBN: 978-2-35500-018-8)
B. Kheradmand Boroujeni, C. Piguet, Y. Leblebici, "Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing",JOLPE - Vol. 7, N° 2, April 2011
C. Piguet, “Green Electronics”, Keynote Talk at NewCAS, Bordeaux, 27-29 juin 2011
Pronath M., Sobe U., Graupner A., Boehme E., “Conversion and Optimization Flow for Analog IP Porting”, DAC Design Automation Conference 2011, San Diego, USA, June 2011
Strube G., Ripp A.,“Trends with Analog Mixed-Signal Design”, Analog 2011 Conference, Erlangen, Germany, November 2011
Neubert R., Rotter P., “Parameter Calibration and Cascaded Simulations - Infineon”, MUGM MunEDA User Group Meeting 2011, Munich, Germany, November 2011
U. Roy, E. Sangiorgi, C. Fiegna. (2010). "Self-Heating Effects in Analog Bulk and SOI CMOS Circuits." 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology Proceedings. 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology. Shanghai, China. November 1-4, 2010. (pp. 1782 - 1785). ISBN: 978-1-4244-5799-1. : IEEE Press.
Participation to Conferences and Workshops
International conference “Moscow-Bavarian Joint Advanced Student School”, Zelenograd, Russia, March 21-25, 2011 - 3 reports
55th International Conference on Electronics, Telecommunications, Computers, Automatic Control and Nuclear Engineering (ETRAN’11), Banja Vrućica, Serbia, June 6-9, 2011 - 2 reports
8th International Conference of “Semiconductor Micro- and Nanoelectronics”, Yerevan, Armenia, July 1-3, 2011 - 2 reports
ASIA Power Architecture Conference, Shenzhen, China, September 1, 2011 - 1 report
9th IEEE East-West Design & Test Symposium (EWDTS’11), Sevastopol, Ukraine, September 9-12,
2011 - 1 report
International conference “Education, Science and Economics at Universities. Integration to International Educational Area”, Yerevan, Armenia, September 26-30, 2011 - 1 report
6th IEEE International Design and Test Workshop (IDT) in Conjunction with IEEE International Conference on Electronics, Circuits and Systems (ICECS), Beirut, Lebanon, December 10-14, 2011 - 1 report
DATE-11: IEEE Design Automation and Test in Europe
Grenoble, France, March 2011.
GLSVLSI-11: ACM/IEEE Great Lakes Symposium on VLSI,
Lausanne, Switzerland, May 2011.
ISCAS-11: IEEE International Conference on Circuits and Systems,
Rio de Janeiro, Brazil, May 2011.
DAC-11: ACM/IEEE Design Automation Conference,
San Diego, CA, June 2011.
ISLPED-11: ACM/IEEE 2010 International Symposium on Low Power Electronics and Design,
Fukuoka, Japan, August 2011.
PATMOS-11: IEEE International Workshop on Power and Timing Modeling, Optimization and
Simulation, Madrid, Spain, September 2011.
THERMINIC 2011: International Workshop on Thermal Investigation of ICs and Systems,
Paris, France, September 2011.
ICCAD-11: IEEE/ACM International Conference on Computer-Aided Design,
San Jose, CA, November 2011.
SEMI-Therm-11: 27th Annual IEEE Thermal Measurement, Modeling and Management Symposium,
San Jose, CA, USA, March 20-24.
A. Burenkov, “TCAD Simulations of Nano-CMOS Including Self-Heating,” contribution to Therminator Tutorial at Intel Mobile Communication
Munich (Germany), Sept. 23, 2011
THERMINATOR MunEDA - Workshop and Training hosted by NXP Hamburg 2011 Dec 06-07;
2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology,
Shanghai, China
2011 Ultimate Integration on Silicon Conference
Cork, Ireland
Other presentations (courses, seminars, etc.)
Chan-Su Yun, Tommaso Cilento, Guenther Zandler, “TCAD: Modeling of CMOS Degradation Mechanisms and Modeling/Calibration of FinFET Devices including Thermal Effects”, Therminator tutorial, Sept. 23, 2011, Munich (Germany)
Vazgen Melikyan, “Thermal and Electro-Thermal Simulation: Achievements and Trends”, 8th International Conference of “Semiconductor Micro- and Nanoelectronics”, July 1-3 2011, Yerevan, Armenia
Vazgen Melikyan, “Methods of Low Power IC Design: Development Trends and Challenges”, Moscow-Bavarian Joint School Conference, March 20-27 2011, Zelenograd, Russia
Shushan Karapetyan, “Low Power Design Methods: Design Flows and Kits”, Moscow-Bavarian Joint School Conference, March 20-27 2011, Zelenograd, Russia
Shushan Karapetyan, Vazgen Melikyan, “Low power design tutorial with 90nm Educational Design Kit”, Moscow-Bavarian Joint School Conference, March 20-27 2011, Zelenograd, Russia
Enrico Macii, “Power-Gating for Leakage Control and Beyond in Nanometer CMOS Circuits”, Keynote speech at IEEE Prime Asia 2011 Macau, China, October 6, 2011.
Enrico Macii, “Power Analysis and Low Power Design”, ALARI Master Course, Lugano, Switzerland, February 2011.
Andrea Calimera, Alberto Macii, “Thermal-Aware Design Techniques for Digital ICs - Basics”, Therminator Course, Torino, Italy, December 2011.
Andrea Calimera, Alberto Macii, “Circuit- and Physical-Level Thermal-Aware Design Techniques for Digital ICs”, Therminator Course, Torino, Italy, December 2011.
Sven Rosinger, Malte Metzdorf, Patrick Knocke, “High-level Thermal Estimation Flow”, IEEE Xplore - Educational Courses.
Joachim Assenmacher, ”Comparison of compact modeling strategies between BSIM and PSP incl. Temperature modeling”, Therminator tutorial, Sept. 23, 2011, Munich (Germany)
Christian Pach, Klaus von Arnim, “Low Power CMOS technologies: A digital view”, Therminator tutorial, Sept. 23, 2011, Munich (Germany)
C. Piguet, “Microelectronics for Systems-on-Chips”, EPFL Course, winter 2011 semester
C. Piguet, “Microelectronics”, ALaRI Course, winter 2011
THERMINATOR Joined Contribution Synopsys-MunEDA at MTF Korea 2011 Jan 21 Seoul Korea hosted by MunEDA: Synopsys Custom and Analog Mixed-Signal Overview & MunEDA WiCkeD Integration (incl. WiCkeD Integration Demo into Synopsys Hspice, CustomSim (HSIM, NanoSim, XA) and CustomDesigner) http://www.muneda.com/User-Group-Meetings_Korea-2011
THERMINATOR MunEDA –Workshop and Training hosted by STMicroelectronics Catania 2011 Feb 26-29: Participants: STMicroelectronics, MunEDA
THERMINATOR MunEDA-Workshop and Training hosted by STMicroelectronics Crolles 2011 Sep 05-09; Participants: STMicroelectronics, MunEDA
THERMINATOR MunEDA-Workshop and Training hosted by STMicroelectroncis Castelletto 2011 Oct 05-06; Participants: STMicroelectronics, MunEDA
THERMINATOR MunEDA-Workshop and Training hosted by Infineon Villacon 2011 Nov 07-09; Participants: Infineon, MunEDA
THERMINATOR MunEDA- Workshop and Training hosted by NXP Hamburg 2011 Dec 06-07; Participants: NXP, Fraunhofer, MunEDA
R. Guerrieri, “Design of electronic systems”, University Of Bologna course, spring 2011 semester
R. Guerrieri, “Digital signal processing Architectures”, University Of Bologna course, spring 2011 semester
Therminic 2011, Therminator Special Sessions
Paris, 27-29. September 2011. – participants: 80
Therminator Special Session I.
1. An Analog Behavioral Thermal Macro-model Aimed at Representing an Elementary Portion of a Discrete IGBT Power Device (Gaetano Bazzano, Daniela Grazia Cavallaro, Giuseppe Greco)
2. Self-heating Effects in Nano-scaled MOSFETs and Thermal Aware Compact Models (Alex Burenkov, Jürgen Lorenz)
3. 3D Electro-Thermal Simulations of Analog ICs carried out with Standard CAD
tools and Verilog-A (Jean-Christophe Krencker, Jean-Baptiste Kammerer, Yannick Hervé and Luc Hébrard)
4. Modeling of Thermally Induced Skew Variations in Clock Distribution Network
(Alessandro Sassone, Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii and Massimo Poncino)
Therminator Special Session II.
1. Improved power modeling in logi-thermal simulation (András Timár, György Bognár, Márta Rencz)
2. A Novel Simulation Environment Enabling Multilevel Power Estimation of Digital Systems (Gergely Nagy, András Poppe)
3. Thermal Modeling of 3D Stacks for Floorplanning (Sven Reitz, Andy Heinig, Roland Martin, Jörn Stolle, Andreas Wilde)
4. High Temperature Calibration of a Compact Model for GaN-on-Si Power Switches (Steve Stoffels, Denis Marcon, Karen Geens, Xuanwu Kang, Geert Van Der Plas, Marleen Van Hove, Stefaan Decoutere)
5. Single-Chip Cloud Computer Thermal Model (Mohammad Sadegh Sadri, Andrea Bartolini, Luca Benini)
FIRST YEAR ACTIVITY
Publications
Calimera A., Bahar R.I, Macii E., Poncino M.,
“Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence,”
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, , 2010, Vol. 18,ISSN: 1063-8210
Calimera A., Bahar R.I, Macii E., Poncino M.,
“Dual-Vt assignment policies in ITD-aware synthesis,”
MICROELECTRONICS JOURNAL, 2010, ISSN: 0959-83242010
Calimera A., Bahar R.I, Macii E., Poncino M.,
“Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverted Temperature Depedence,”
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, Vol. 18, ISSN: 1063-8210
Calimera A., Macii A., Macii E., Poncino M., Rinaudo S.,
“THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future,”
THERMINIC 2010, Barcelona, Spain, October 2010.
Caldera M., Calimera A., Macii A., Macii E., Poncino M.,
“Minimizing temperature sensitivity of dual-Vt CMOS circuits using simulated-annealing on ISING-like models,”
THERMINIC 2010, Barcelona, Spain, October 2010.
M. Braccioli, A. Scholten, G. Curatola, E. Sangiorgi, and C. Fiegna,
Proc. Ultimate Integration on Silicon Conf., 81 (2010).
A.J. Scholten, G.D.J. Smit, R.M.T. Pijper, L.F. Tiemeijer, A. Mercha, and D.B.M. Klaassen,
IEDM Tech. Digest, 190 (2010).
D.L. John, F. Allerstam, T. Roedle, S.K. Murad, and G.D.J. Smit,
IEDM Tech. Digest, 186 (2010).
S. Rosinger, M. Metzdorf, D. Helms and W. Nebel,
“Behavioral-Level Thermal- and Aging-Estimation Flow”,
Proc. of 12th Latin-American Test Workshop (LATW), 2011.
G.Greco, S. Rinaudo
“Automatic Layout Optimization of Power Discrete Devices Using Innovative Distributed Model Techniques”
ECMI 2010, Wuppertal, Germany, July 2010.
G.Bazzano, D. G. Cavallaro, G. Greco, A. Grimaldi, S. Rinaudo,
“2D Thermal Propagation Analysis of Discrete Power Devices Based on an Innovative Distributed Model Technique and CAD Framework”,
THERMINIC 2010, Barcelona, Spain, October 2010.
A. Timár, A. Poppe, M. Rencz,
“A Novel Approach of Logi-thermal Simulation Methodology and Implementation for ASIC Designs”,
Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'10), Wroclaw, Poland, June 2010.
A. Timár, Gy. Bognár, A. Poppe, M. Rencz,
“Electro-thermal co-simulation of ICs with runtime back-annotation capability”,
THERMINIC 2010, Barcelona, Spain, October 2010.
A. Timár, Gy. Bognár, A. Poppe, M. Rencz,
“Electro-thermal co-simulation of ICs with runtime back-annotation capability”,
International Journal of Microelectronics and Computer Science
Volume 1, Number 3, 2010, pp. 287-292, ISSN 2080-8755
R. Jancke, A. Wilde, R. Martin, S. Reitz,
“Modeling and Simulation of Electro-Thermal Interaction Effects in Electronic Circuits and Devices”,
Fraunhofer Multiphysics Konferenz 2010, Bonn, Germany, June 2010.
R. Jancke, A. Wilde, R. Martin, S. R. P. Schneider,
“Simulation of Electro-Thermal Interaction.”,
Electronics System Integration Technology Conference, ESTC 2010, Berlin, Germany, September 2010.
Participation to Conferences and Workshops
DATE-10: IEEE Design Automation and Test in Europe
Dresden, Germany, March 2010.
GLSVLSI-10: ACM/IEEE Great Lakes Symposium on VLSI,
Providence, RI, May 2010.
ISCAS-10: IEEE International Conference on Circuits and Systems,
Paris, France, May 2010.
DAC-10: ACM/IEEE Design Automation Conference,
Anaheim, CA, June 2010.
ISLPED-10: ACM/IEEE 2010 International Symposium on Low Power Electronics and Design, Austin,
TX, August 2010.
PATMOS-10: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, Grenoble, France, September 2010.
THERMINIC 2010: International Workshop on Thermal Investigation of ICs and Systems, Barcelona, Spain, October 2010.
ICCAD-10: IEEE/ACM International Conference on Computer-Aided Design,
San Jose, CA, November 2010.
Other presentations (courses, seminars, etc.)
Macii E.,
“Power Analysis and Low Power Design”,
ALARI Master Course,
Lugano, Switzerland, January 2010.
Macii E.,
“Leakage power minimization and thermal effects compensation in digital nanometer CMOS circuits”,
First IEEE CASS Summer School, Physical Design of Reliable Circuits,
Porto Alegre, Brazil, January 2010.
Macii E.,
“Thermal-Aware Design: Challenges and Advanced Solutions”,
Microelectronics Summer School,
Florianopolis, Brazil, May 2010.
Calimera A., Macii A., Macii E., Poncino M.,
“Modeling, design and CAD for low-leakage nanometer CMOS circuits and systems”,
Conference Tutorial,
ISCAS-10: IEEE International Conference on Circuits and Systems,
Paris, France, May 2010.
Atienza D., Ayala J.L., Calimera A.,
“Thermal Modeling and Management for 2D/3D MPSoC Platforms”,
Conference Tutorial,
ICECS 2010: IEEE International Conference on Electronics, Circuits, and Systems,
Athens, Greece, December 2010.
K. von Arnim,
“Device options for low power technologies and SOC implementation”,
Technology Short Course, Symposium on VLSI Technology, Honolulu, June 2010.
C. Piguet,
“Low-Power Systems-on-Chips”, ENSEIRB, Bordeaux, January 2011.